Medical image encryption techniques: a technical survey and potential challenges

Among the most sensitive and important data in telemedicine systems are medical images. It is necessary to use a robust encryption method that is resistant to cryptographic assaults while transferring medical images over the internet. Confidentiality is the most crucial of the three security goals for protecting information systems, along with availability, integrity, and compliance. Encryption and watermarking of medical images address problems with confidentiality and integrity in telemedicine applications. The need to prioritize security issues in telemedicine applications makes the choice of a trustworthy and efficient strategy or framework all the more crucial. The paper examines various security issues and cutting-edge methods to secure medical images for use with telemedicine systems

An Efficient Deep-Learning-Based Detection and Classification System for Cyber-Attacks in IoT Communication Networks

With the rapid expansion of intelligent resource-constrained devices and high-speed communication technologies, the Internet of Things (IoT) has earned wide recognition as the primary standard for low-power lossy networks (LLNs). Nevertheless, IoT infrastructures are vulnerable to cyber-attacks due to the constraints in computation, storage, and communication capacity of the endpoint devices. From one side, the majority of newly developed cyber-attacks are formed by slightly mutating formerly established cyber-attacks to produce a new attack that tends to be treated as normal traffic through the IoT network. From the other side, the influence of coupling the deep learning techniques with the cybersecurity field has become a recent inclination of many security applications due to their impressive performance. In this paper, we provide the comprehensive development of a new intelligent and autonomous deep-learning-based detection and classification system for cyber-attacks in IoT communication networks that leverage the power of convolutional neural networks, abbreviated as IoT-IDCS-CNN (IoT based Intrusion Detection and Classification System using Convolutional Neural Network). The proposed IoT-IDCS-CNN makes use of high-performance computing that employs the robust Compute Unified Device Architectures (CUDA) based Nvidia GPUs (Graphical Processing Units) and parallel processing that employs high-speed I9-core-based Intel CPUs. In particular, the proposed system is composed of three subsystems: a feature engineering subsystem, a feature learning subsystem, and a traffic classification subsystem. All subsystems were developed, verified, integrated, and validated in this research. To evaluate the developed system, we employed the Network Security Laboratory-Knowledge Discovery Databases (NSL-KDD) dataset, which includes all the key attacks in IoT computing. The simulation results demonstrated a greater than 99.3% and 98.2% cyber-attack classification accuracy for the binary-class classifier (normal vs. anomaly) and the multiclass classifier (five categories), respectively. The proposed system was validated using a K-fold cross-validation method and was evaluated using the confusion matrix parameters (i.e., true negative (TN), true positive (TP), false negative (FN), false positive (FP)), along with other classification performance metrics, including precision, recall, F1-score, and false alarm rate. The test and evaluation results of the IoT-IDCS-CNN system outperformed many recent machine-learning-based IDCS systems in the same area of study

Forecasting the Number of Monthly Active Facebook and Twitter Worldwide Users Using ARMA Model

In this study, an Auto-Regressive Moving Average (ARMA) Model with optimal order has been developed to estimate and forecast the short term future numbers of the monthly active Facebook and Twitter worldwide users. In order to pickup the optimal estimation order, we analyzed the model order vs. the corresponding model error in terms of final prediction error. The simulation results showed that the optimal model order to estimate the given Facebook and Twitter time series are ARMA[5, 5] and ARMA[3, 3], respectively, since they correspond to the minimum acceptable prediction error values. Besides, the optimal models recorded a high-level of estimation accuracy with fit percents of 98.8% and 96.5% for Facebook and Twitter time series, respectively. Eventually, the developed framework can be used accurately to estimate the spectrum for any linear time series

A Tiny RSA Cryptosystem based on Arduino Microcontroller Useful for Small Scale Networks

AbstractRSA Cryptography is a well-known example of public key cryptographic algorithms that involves robust encryption/decryption processes. In this paper, a microcontroller based RSA is designed and proposed. Arduino Mega2560R3 microcontroller supported with external memory and a screen touch LCD as well as a double keypad has been used under the programming of C language to implement the proposed RSA coprocessor with 32 bits. It was found that the trade of between message size and the encryption time can be drawn as a liner relationship according to the block size of the encryption phase. However, such design with a MCU provided with a small solar cell (and off course with a backup battery) as well as small block sizes is considered useful for the use in wireless sensor network (WSN) applications due to the ease of connecting the MCU to the WSN which as well avoid the processing time of encryption/decryption processes that could be executed by the MCU instead of the life limited sensors

Implementing a lightweight Schmidt-Samoa cryptosystem (SSC) for sensory communications

One of the remarkable issues that face wireless sensor networks (WSNs) nowadays is security. WSNs should provide a way to transfer data securely particularly when employed for mission-critical purposes. In this paper, we propose an enhanced architecture and implementation for 128-bit Schmidt-Samoa cryptosystem (SSC) to secure the data communication for wireless sensor networks (WSN) against external attacks. The proposed SSC cryptosystem has been efficiently implemented and verified using FPGA modules by exploiting the maximum allowable parallelism of the SSC internal operations. To verify the proposed SSC implementation, we have synthesized our VHDL coding using Quartus II CAD tool targeting the Altera Cyclone IV FPGA EP4CGX22CF19C7 device. Hence, the synthesizer results reveal that the proposed cryptographic FPGA processor recorded an attractive result in terms of critical path delay, hardware utilization, maximum operational frequency FPGA thermal power dissipation for low-power applications such as the wireless sensor networks

Hardware architectures & designs for projective elliptic curves point addition operation using variable levels of parallelism

Although ECC protocol is considered one of the most secure schemes for information security; it also suffers in its arithmetic computations from the modular inversion operation which is known to be time consuming operation. In the addition operation, Many ECC designs that use projective coordinates over GF (p) have not considered a balance between area, hardware utilization, and performance factors which is important in many ECC applications. In this research we proposed to use the projective coordinates systems to compute the ECC point addition operation with no inversion operations due to the ability to convert each inversion to several multiplication operations that can be applied in parallel. We also present several architectures and design choices for point addition operation that will help to build ECC Coprocessor. These architectures consider different levels of parallelism which may give different choices in ECC design in terms of time and space. This paper proposes the different hardware architectures to design ECC Processor by varying the degree of parallelization benefiting from the inherent parallelism for ECC addition operation. It was shown that the throughput of the design with 4 parallel multipliers enhanced the system performance by 400% and 340% for both projections (X/Z, Y/Z), and (X/Z2, Y/Z3) respectively while the design with 5 parallel multipliers is considered the best fit for projection (X/Z, Y/Z2) due its ability to best utilize and parallelize the hardware arithmetic operations. However, the projection (X/Z, Y/Z) when applied using 4 parallel multipliers gave the best results in terms of hardware utilization, parallelization enhancements and cost factor which make it the first choice when you design the ECC Coprocessor using projective coordinates. A trade-off between security, area and performance is which control the ECC Coprocessor design, the more parallelization you make the more area needed the less time required which will lead to a better performance

FPGA implementation of variable precision Euclid’s GCD algorithm

Introduction: Euclid's algorithm is well-known for its efficiency and simple iterative to compute the greatest common divisor (GCD) of two non-negative integers. It contributes to almost all public key cryptographic algorithms over a finite field of arithmetic. This, in turn, has led to increased research in this domain, particularly with the aim of improving the performance throughput for many GCD-based applications. Methodology: In this paper, we implement a fast GCD coprocessor based on Euclid's method with variable precisions (32-bit to 1024-bit). The proposed implementation was benchmarked using seven field programmable gate arrays (FPGA) chip families (i.e., one Altera chip and six Xilinx chips) and reported on four cost complexity factors: the maximum frequency, the total delay values, the hardware utilization and the total FPGA thermal power dissipation. Results: The results demonstrated that the XC7VH290T-2-HCG1155 and XC7K70T-2-FBG676 devices recorded the best maximum frequencies of 243.934 MHz down to 39.94 MHz for 32-bits with 1024-bit precisions, respectively. Additionally, it was found that the implementation with different precisions has utilized minimal resources of the target device, i.e., a maximum of 2% and 4% of device registers and look-up tables (LUT’s). Conclusions: These results imply that the design area is scalable and can be easily increased or embedded with many other design applications. Finally, comparisons with previous designs/implementations illustrate that the proposed coprocessor implementation is faster than many reported state-of-the-art solutions. This paper is an extended version of our conference paper [1]